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Re-evaluation of the RISC I

Re-evaluation of the RISC I Contributions... Re-evaluation of the RISC I J. L. Heath, North Dakota State University Fargo, ND 58105 1. II~IKI~JCTION Recently reported research <3> indicates that the RISC I, a reduced instruction set con~puter, is able to outperform conventional processors. The validity of these results has, however, been questioned <7> since factors not directly related to the size and s ~ c d of the instruction set may have been utilized to the RISC I's advantage. By removing these extraneous factors, and re-evaluating the RISC I, this paper hopes to more completely evaluate the reduced instruction set computer. 2. BACKGR~JND The Reduced Instruction Set Computer is a relatively new concept in c(mputer architecture. The most publicized example of the reduced instruction set design philosophy is the RISC I, a 32 bit microprocessor which has been developed at the University of California, Berkeley. The results reported for the RISC I, when compared to conventional microprocessors, indicate that the RISC I offers improved performance when executing compiled C programs. The tests used in this evaluation compared the performance of the RISC I to the MC68000, the Z8000, and several other processors. The performance of these processors was measured via benchmark programs which http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM SIGARCH Computer Architecture News Association for Computing Machinery

Re-evaluation of the RISC I

ACM SIGARCH Computer Architecture News , Volume 12 (1) – Mar 1, 1984

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Publisher
Association for Computing Machinery
Copyright
Copyright © 1984 by ACM Inc.
ISSN
0163-5964
DOI
10.1145/641602.641603
Publisher site
See Article on Publisher Site

Abstract

Contributions... Re-evaluation of the RISC I J. L. Heath, North Dakota State University Fargo, ND 58105 1. II~IKI~JCTION Recently reported research <3> indicates that the RISC I, a reduced instruction set con~puter, is able to outperform conventional processors. The validity of these results has, however, been questioned <7> since factors not directly related to the size and s ~ c d of the instruction set may have been utilized to the RISC I's advantage. By removing these extraneous factors, and re-evaluating the RISC I, this paper hopes to more completely evaluate the reduced instruction set computer. 2. BACKGR~JND The Reduced Instruction Set Computer is a relatively new concept in c(mputer architecture. The most publicized example of the reduced instruction set design philosophy is the RISC I, a 32 bit microprocessor which has been developed at the University of California, Berkeley. The results reported for the RISC I, when compared to conventional microprocessors, indicate that the RISC I offers improved performance when executing compiled C programs. The tests used in this evaluation compared the performance of the RISC I to the MC68000, the Z8000, and several other processors. The performance of these processors was measured via benchmark programs which

Journal

ACM SIGARCH Computer Architecture NewsAssociation for Computing Machinery

Published: Mar 1, 1984

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