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Prefetch unit for vector operations on scalar computers Ivan Sklen£~ Institute of Physics CSAV, Cukrovarnickg 10, CS-162 00 Praha 6 e-mail:SKLENAR at C S P G F U l l . B I T N E T May 27, 1992 Abstract Current caches are not adequate for vector operations. A new kind of support for vector operations, called prefetch unit, is designed to improve the performance of the scalar (SISD) processors. The prefetch unit can be used for any SISD architecture and also for many kinds of MIMD architectures. It may run in parallel and asynchronously with other parts of processor. It keeps trace of the history of memory references, and therefore initializes rarely any superfluous prefetches. Introduction High-speed vector processors achieve their peak performance by exploiting their high memory bandwidth using the regular allocation of vector elements in the main memory. There are no comparable facilities in SISD processors. To improve memory-processor traffic, almost all current SISD processors use caches. Caches benefit mostly by the time locality of data, but when cache lines (blocks) are long, they use also space locality to some limited extent. In fact, vector data do not fit well into that philosophy. When
ACM SIGARCH Computer Architecture News – Association for Computing Machinery
Published: Sep 1, 1992
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