Access the full text.
Sign up today, get DeepDyve free for 14 days.
Saurabh Adya, Shubhyant Chaturvedi, Jarrod Roy, D. Papa, I. Markov (2004)
Unification of partitioning, placement and floorplanningIEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang (2007)
Temporal floorplanning using the three-dimensional transitive closure subGraphACM Trans. Design Autom. Electr. Syst., 12
(2007)
Virtex 5 - family overview
J. Stankovic (1996)
Strategic directions in real-time and embedded systemsACM Comput. Surv., 28
(2010)
ACM Transactions on Reconfigurable Technology and Systems
S. Sait, H. Youssef (1995)
VLSI Physical Design Automation - Theory and Practice, 6
A. Donato, Fabrizio Ferrandi, M. Redaelli, M. Santambrogio, D. Sciuto (2005)
Exploiting partial dynamic reconfiguration for SoC design of complex application on FPGA platforms
(2007)
Virtex II - family overview
Jarrod Roy, Saurabh Adya, D. Papa, I. Markov (2006)
Min-cut floorplacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25
(2006)
Early access partial reconfiguration user guide. Xilinx Incorporation
M. Vasilko (1999)
DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems
Heiko Kalte, Gareth Lee, Mario Porrmann, U. Rückert (2005)
REPLICA: a bitstream manipulation filter for module relocation in partial reconfigurable systems19th IEEE International Parallel and Distributed Processing Symposium
S. Fekete, Ekkehard Köhler, J. Teich (2001)
Optimal FPGA module placement with temporal precedence constraintsProceedings Design, Automation and Test in Europe. Conference and Exhibition 2001
(2007)
Virtex 5 -family overview. Xilinx Incorporation
Yan Feng, D. Mehta (2006)
Heterogeneous floorplanning for FPGAs19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)
(2007)
Xilinx application note 290
(2008)
Received October
(1999)
CoreConnect(TM) bus architecture
(2007)
Virtex II -family overview. Xilinx Incorporation
N. Sherwani (1995)
VLSI Physical Design Automation
L. Singhal, E. Bozorgzadeh (2006)
Multi-layer Floorplanning on a Sequence of Reconfigurable Designs2006 International Conference on Field Programmable Logic and Applications
(2002)
MicroBlaze hardware reference guide
Saurabh Adya, I. Markov (2003)
Fixed-outline floorplanning: enabling hierarchical designIEEE Trans. Very Large Scale Integr. Syst., 11
(2007)
Xilinx application note 290. Xilinx Incorporation
K. Bazargan, R. Kastner, M. Sarrafzadeh (1999)
3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing SystemsDesign Automation for Embedded Systems, 5
S. Corbetta, Fabrizio Ferrandi, M. Morandi, M. Novati, M. Santambrogio, D. Sciuto (2007)
Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable SystemIEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
H. Murata, K. Fujiyoshi, S. Nakatake, Y. Kajitani (1996)
VLSI module placement based on rectangle-packing by the sequence-pairIEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15
Rajesh Gupta, G. Micheli (2008)
Co-Synthesis of Hardware and Software for Digital Embedded Systems
(2006)
Early access partial reconfiguration user guide
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang (2004)
Temporal floorplanning using the T-tree formulationIEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.
Placement and Floorplanning in Dynamically Recon gurable FPGAs ALESSIO MONTONE Politecnico di Milano MARCO D. SANTAMBROGIO Massachusetts Institute of Technology DONATELLA SCIUTO Politecnico di Milano and SEDA OGRENCI MEMIK Northwestern University The aim of this article is to describe a complete partitioning and oorplanning algorithm tailored for recon gurable architectures deployable on FPGAs and considering communication infrastructure feasibility. This article proposes a novel approach for resource- and recon guration- aware oorplanning. Different from existing approaches, our oorplanning algorithm takes speci c physical constraints such as resource distribution and the granularity of recon guration possible for a given FPGA device into account. Due to the introduction of constraints typical of other problems like partitioning and placement, the proposed approach is named oorplacer in order to underline the great differences with respect to traditional oorplanners. These physical constraints are typically considered at the later placement stage. Different aspects of the problems have been described, focusing particularly on the FPGAs resource heterogeneity and the temporal dimension typical of recon gurable systems. Once the problem is introduced a comparison among related works has been provided and their limits have been pointed out. Experimental results proved the validity of the proposed approach. Categories
ACM Transactions on Reconfigurable Technology and Systems (TRETS) – Association for Computing Machinery
Published: Nov 1, 2010
Read and print from thousands of top scholarly journals.
Already have an account? Log in
Bookmark this article. You can see your Bookmarks on your DeepDyve Library.
To save an article, log in first, or sign up for a DeepDyve account if you don’t already have one.
Copy and paste the desired citation format or use the link below to download a file formatted for EndNote
Access the full text.
Sign up today, get DeepDyve free for 14 days.
All DeepDyve websites use cookies to improve your online experience. They were placed on your computer when you launched this website. You can change your cookie settings through your browser.