PicoServer: Using 3D Stacking Technology To Build Energy Ef cient Servers TAEHO KGIL University of Michigan, Intel ALI SAIDI University of Michigan NATHAN BINKERT HP Labs STEVE REINHARDT University of Michigan, AMD KRISZTIAN FLAUTNER ARM and TREVOR MUDGE University of Michigan This article extends our prior work to show that a straightforward use of 3D stacking technology enables the design of compact energy-ef cient servers. Our proposed architecture, called PicoServer, employs 3D technology to bond one die containing several simple, slow processing cores to multiple memory dies suf cient for a primary memory. The multiple memory dies are composed of DRAM. This use of 3D stacks readily facilitates wide low-latency buses between processors and memory. These remove the need for an L2 cache allowing its area to be re-allocated to additional simple cores. The additional cores allow the clock frequency to be lowered without impairing throughput. Lower clock frequency means that thermal constraints, a concern with 3D stacking, are easily satis ed. We extend our original analysis on PicoServer to include: (1) a wider set of server workloads, (2) the impact of multithreading, and (3) the on-chip DRAM architecture and system memory usage. PicoServer is intentionally simple, requiring
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PicoServer: Using 3D stacking technology to build energy efficient servers
Kgil, Taeho; Saidi, Ali; Binkert, Nathan; Reinhardt, Steve; Flautner, Krisztian; Mudge, Trevor
Follow ACM Journal on Emerging Technologies in Computing Systems (JETC)
, Volume 4 (4)
Association for Computing Machinery – Oct 1, 2008
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