Performance Evaluation and Validation of Microprocessors Pradip Bose IBM T. J. Watson Research Center F! 0. Box 218 Yorktown Heights, NY 10598 914-945-3478 pboseQus.ibm.com 1. ABSTRACT In this paper, we provide an overview of the current challenges in pre-silicon evaluation and validation of processors. This is based largely on the author s own perspective, developed over many years of experience as a performance architect in IBM s PowerPCTM design projects. 1.1 Keywords Performanceevaluation, validation, processordesign. The RTL model, usually coded in a hardware description language, or HDL (e.g. Verilog or VHDL) captures the logical behavior of the entire chip: both in terms of function and cycle-by-cycle pipeline flow timing. It is this model that is subjected to simulation-basedfunctional validation prior to actual tape-out of the processor.Such a model operates at a relatively slow speedof tens of instructions per second on a single workstation. Of course, to facilitate pre-silicon validation, a network of workstations is typically used to speedup simulation runs. There are several problems with the above methodology as we try to scaleup our toolsetsto meet future needs: The design abstraction at the CPI timer level is already too complex to take model correctnessfor granted. Validation by
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Performance evaluation and validation of microprocessors
Bose, Pradip
Follow ACM SIGMETRICS Performance Evaluation Review
, Volume 27 (1)
Association for Computing Machinery – Jun 1, 1999
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