Parametric Yield Management for 3D ICs: Models and Strategies for Improvement CESARE FERRI, SHERIEF REDA, and R. IRIS BAHAR Brown University Three-Dimensional (3D) Integrated Circuits (ICs) that integrate die with Through-Silicon Vias (TSVs) promise to continue system and functionality scaling beyond the traditional geometric 2D device scaling. 3D integration also improves the performance of ICs by reducing the communication time between different chip components through the use of short TSV-based vertical wires. This reduction is particularly attractive in processors where it is desirable to reduce the access time between the main logic die and the L2 cache or the main memory die. Process variations in 2D ICs lead to a drop in parametric yield (as measured by speed, leakage and sales pro ts), which forces manufacturers to speed bin their chips and to sell slow chips at reduced prices. In this paper we develop a model to quantify the impact of process variations on the parametric yield of 3D ICs, and then we propose a number of integration strategies that use a graph-theoretic framework to maximize the performance, parametric yield and pro ts of 3D ICs. Comparing our proposed strategies to current yield-oblivious methods, it is demonstrated that
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Parametric yield management for 3D ICs: Models and strategies for improvement
Ferri, Cesare; Reda, Sherief; Bahar, R. Iris
Follow ACM Journal on Emerging Technologies in Computing Systems (JETC)
, Volume 4 (4)
Association for Computing Machinery – Oct 1, 2008
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