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Journals ACM SIGARCH Computer Architecture News Volume 35 Issue 5

Recent embedded systems have switched to fully programmable parallel architectures. To make sure all corner cases usually present in real applications are supported and efficiently implemented in this switch of implementation, new solutions must be found. We introduce the integral parallel architecture (IPA) as a solution supporting intensive data computation in System-on-a-chip (Soc) implementations, fitting in a small area , and requiring low power . An IPA supports naturally all three possible styles of parallelism: data, time , and speculative . As an illustrative example, we present the BA1024 chip, a fully programmable SoC designed by BrightScale, Inc. for HDTV codecs. Its main performance figures include 60 GOPS/Watt and 2 GOPS/mm 2 , representing an efficient IPA approach for embedded computation.

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Not multi-, but many-core: designing integral parallel architectures for embedded computation

Maliţa, Mihaela; Ştefan, Gheorghe; Thiébaut, Dominique
ACM SIGARCH Computer Architecture News , Volume 35 (5)
Association for Computing Machinery – Dec 1, 2007

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