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Journals ACM Journal on Emerging Technologies in... Volume 4 Issue 4

Multilayer Stacking Technology Using Wafer-to-Wafer Stacked Method NOBUAKI MIYAKAWA, EIRI HASHIMOTO, TAKANORI MAEBASHI, NATSUO NAKAMURA, YUTAKA SACHO, SHIGETO NAKAYAMA, and SHINJIRO TOYODA Honda Research Institute Japan We have developed a new three-dimensional stacking technology using the wafer-to-wafer stacked method. Electrical conductivity between each wafer is almost 100% and contact resistance is less than 0.7 between a through-silicon via (TSV) and a microbump. We have also created a prototype of a three-layer stacking device using our technology, where each wafer for the stacking is fabricated by using 0.18um CMOS technology based on 8-inch wafers. The device is operated by two times the frequency of the multichip module (MCM) device case using a two-dimensional device with identical functions and minimally different power consumption. The yields obtained from the results comprising all functional tests are over 60%. Categories and Subject Descriptors: B.2.2 [Arithmetic and Logic Structures]: Performance Analysis and Design Aids ”Veri cation; B.2.4 [Arithmetic and Logic Structures]: High-Speed Arithmetic ”Cost/Performance; B.4.3 [Input/Output and Data Communications]: Interconnections ”Physical structures; B.4.5 [Input/Output and Data Communications]: Reliability, Testing, and Fault Tolerance ”Hardware reliability; B.7.1 [Integrated Circuits]: Types and Design Styles ”Advanced technologies; B.8.0 [Performance and Reliability]: General General Terms: Design, Performance, Reliability, Veri

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