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References (26)
-
Jared Smolens, Brian Gold, Jangwoo Kim, B. Falsafi, J. Hoe, A. Nowatzyk (2004)
Fingerprinting: bounding soft-error detection latency and bandwidth -
D. Wood, Garth Gibson, R. Katz (1990)
Verifying a multiprocessor cache controller using random test generationIEEE Design & Test of Computers, 7
-
Daniel Sorin, Manoj Plakal, A. Condon, M. Hill, Milo Martin, D. Wood (2002)
Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence ProtocolIEEE Trans. Parallel Distributed Syst., 13
-
D. Dill, Andreas Drexler, A. Hu, Han Yang (1992)
Protocol verification as a hardware design aidProceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors
-
Lambert Schaelicke (2002)
ML-RSIM Reference Manual -
Systems Performance Evaluation Cooperation. SPEC Benchmarks -
Homayoon Akhiani, Damien Doligez, Paul Harter, L. Lamport, Joshua Scheid, M. Tuttle, Yuan Yu (1999)
Cache Coherence Verification with TLA+ -
Michael Marty, Jesse Bingham, M. Hill, A. Hu, Milo Martin, D. Wood (2005)
Improving multiple-CMP systems using token coherence11th International Symposium on High-Performance Computer Architecture
-
T. Austin, E. Larson, Dan Ernst (2002)
SimpleScalar: An Infrastructure for Computer System ModelingComputer, 35
-
J. Laudon, D. Lenoski (1997)
The SGI Origin: A ccnuma Highly Scalable ServerConference Proceedings. The 24th Annual International Symposium on Computer Architecture
-
(2005)
ACM SIGARCH Computer Architecture News -
N. Binkert (2003)
Network-Oriented Full-System Simulation using M5 -
Carl Mauer, M. Hill, D. Wood (2002)
Full-system timing-first simulation -
D. Lenoski, J. Laudon, K. Gharachorloo, Anoop Gupta, J. Hennessy (1990)
The directory-based cache coherence protocol for the DASH multiprocessor[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture
-
Mikko Lipasti, Harold Cain, Kevin Lepak (2002)
Precise and Accurate Processor Simulation -
Shubhendu Mukherjee, P. Bannon, S. Lang, A. Spink, David Webb (2001)
The Alpha 21364 network architectureHOT 9 Interconnects. Symposium on High Performance Interconnects
-
(2002)
AMD Opteron Shared Memory MP Systems -
Alaa Alameldeen, Milo Martin, Carl Mauer, Kevin Moore, Min Xu, Mark Hill, David Wood, Daniel Sorin (2003)
Simulating a $2M Commercial Server on a $2K PCComputer, 36
-
Milo Martin, M. Hill, D. Wood (2003)
Token Coherence: A New Framework for Shared-Memory MultiprocessorsIEEE Micro, 23
-
Bradford Beckmann, D. Wood (2004)
Managing Wire Delay in Large Chip-Multiprocessor Caches37th International Symposium on Microarchitecture (MICRO-37'04)
-
M. Rosenblum, S. Herrod, E. Witchel, Anoop Gupta (1995)
Complete computer system simulation: the SimOS approachIEEE Parallel Distributed Technol. Syst. Appl., 3
-
Peter Magnusson, M. Christensson, Jesper Eskilson, Daniel Forsgren, Gustav Hållberg, Johan Högberg, F. Larsson, Andreas Moestedt, Bengt Werner (2002)
Simics: A Full System Simulation PlatformComputer, 35
-
Chetana Keltcher, K. McGrath, A. Ahmed, Patrick Conway (2003)
The AMD Opteron Processor for Multiprocessor ServersIEEE Micro, 23
-
Protocol Specifications and Tables for Four Comparable MOESI Coherence Protocols: Token Coherence, Snooping, Directory, and Hammer -
L. Lamport (2002)
Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers -
Free Software Foundation. GNU General Public License (GPL)
- Publisher
- Association for Computing Machinery
- Copyright
- Copyright © 2005 by ACM Inc.
- ISSN
- 0163-5964
- DOI
- 10.1145/1105734.1105747
- Publisher site
- See Article on Publisher Site
Abstract
The Wisconsin Multifacet Project has created a simulation toolset to characterize and evaluate the performance of multiprocessor hardware systems commonly used as database and web servers. We leverage an existing full-system functional simulation infrastructure (Simics 14) as the basis around which to build a set of timing simulator modules for modeling the timing of the memory system and microprocessors. This simulator infrastructure enables us to run architectural experiments using a suite of scaled-down commercial workloads 3. To enable other researchers to more easily perform such research, we have released these timing simulator modules as the Multifacet General Execution-driven Multiprocessor Simulator (GEMS) Toolset, release 1.0, under GNU GPL 9.
Journal
ACM SIGARCH Computer Architecture News – Association for Computing Machinery
Published: Nov 1, 2005