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Journals ACM SIGARCH Computer Architecture News Volume 37 Issue 2

The introduction of multicore microprocessors in the recent years has made it imperative to use cycleaccurate and full-system simulators in the architecture research community. We introduce MPTLsim - a multicore simulator for the X86 ISA that meets this need. MPTLsim is a uop-accurate, cycle-accurate, full-system simulator for multicore designs based on the X86-64 ISA. MPTLsim extends PTLsim, a publicly available single core simulator, with a host of additional features to support hyperthreading within a core and multiple cores, with detailed models for caches, on-chip interconnections and the memory data flow. MPTLsim incorporates detailed simulation models for cache controllers, interconnections and has built-in implementations of a number of cache coherency protocols.

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MPTLsim: a cycle-accurate, full-system simulator for x86-64 multicore architectures with coherent caches

Zeng, Hui; Yourst, Matt; Ghose, Kanad; Ponomarev, Dmitry
ACM SIGARCH Computer Architecture News , Volume 37 (2)
Association for Computing Machinery – Jul 23, 2009

More Info
  • Publisher Association for Computing Machinery
  • Copyright The ACM Portal is published by the Association for Computing Machinery. Copyright © 2010 ACM, Inc.
  • Subject Environments
  • ISSN 0163-5964
  • D.O.I. 10.1145/1577129.1577132
  • Publisher site Get PDF  

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