Microarchitecture Support for Dynamic Scheduling of Acyclic Task Graphs Carl J. Beckmann Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign 465 CSRL, 1308 W. Main St., Urbana, IL. 61801-2307 beckmann@csrd.uiuc.edu Constantine D. Polychronopoulos Kubota Pacific, Inc. 2630 Walsh Ave., Santa Clara, CA. 95051-0905, and Center for Supercomputing Research and Development cdp@kpc.com Abstract-- Any program can be broken into its loop structure, plus acyclic dependence graphs representing the body of each loop or subroutine. The parallelism inherent in these acyclic graphs augments the looplevel parallelism available in the program. This paper presents two algorithms for dynamic scheduling of acyclic task graphs containing both data and control dependences, and describes a microarchitecture which implements these algorithms efficiently. level. While static instruction scheduling can be used to exploit instruction level functional (and loop) parallelism [21] [14] [6], static schedules are based on constant instruction execution times and fixed dependence structure. These techniques face difficulties in dealing with conditional branches and variable instruction execution times, such as memory loads which must traverse a multistage network. This paper investigates algorithms for dynamic scheduling of acyclic task graphs, and hardware support for exploiting instruction-level functional parallelism. We assume the compiler
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