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Journals ACM SIGARCH Computer Architecture News Volume 32 Issue 2

The on-chip communication requirements of manysystems are best served through the deployment of a regularchip-wide network. This paper presents the design of alow-latency on-chip network router for such applications.We remove control overheads (routing and arbitrationlogic) from the critical path in order to minimise cycle-timeand latency. Simulations illustrate that dramatic cycle timeimprovements are possible without compromising routerefficiency. Furthermore, these reductions permit flits to berouted in a single cycle, maximising the effectiveness of therouter's limited buffering resources.

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Low-Latency Virtual-Channel Routers for On-Chip Networks

Mullins, Robert; West, Andrew; Moore, Simon
ACM SIGARCH Computer Architecture News , Volume 32 (2)
Association for Computing Machinery – Mar 2, 2004

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