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Look-Ahead Processors

Look-Ahead Processors Look-Ahead Processors ROBERT M. KELLER Department of Electrical Eng~neerzng, Princeton University, Princeton, New Jersey 085~0 Methods of achieving look-ahead in processing units are discussed. An optimality criterion is proposed, and several schemes are compared against the optimum under varying assumptions. These schemes include existing and proposed machine organizations, and theoretical treatments not mentioned before in this context. The problems of eliminating associative searches in the processor control and the handling of loop-forming decisions are also considered. The inherent limitations of such processors are discussed. Finally, a number of enhancements to look-ahead proces- sors is qualitatively surveyed. Keywords and Phrases: asynchronous computation, computer architecture, computer organization, look-ahead, parallelism, pipelining, schemata CR Categories: 5.24, 5.5, 6.32, 6.33 INTRODUCTION Arithmetic and logical processors in computers of the "second generation" and earlier tended to be unsophisticated insofar as their highly serial nature of instruction execution was concerned. Furthermore, the bottleneck created by a relatively slow core memory with a single-access port made the problem of enhancing the processor's speed uninteresting. With the advent of such techniques as multiple-port interleaved memories, semiconductor memories, and the use of more fast, local registers (either programmable or cache), we have the capability of transmitting operands and http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM Computing Surveys (CSUR) Association for Computing Machinery

Look-Ahead Processors

Keller, Robert M.
ACM Computing Surveys (CSUR) , Volume 7 (4) – Dec 1, 1975
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References (40)

Publisher
Association for Computing Machinery
Copyright
Copyright © 1975 by ACM Inc.
ISSN
0360-0300
DOI
10.1145/356654.356657
Publisher site
See Article on Publisher Site

Abstract

Look-Ahead Processors ROBERT M. KELLER Department of Electrical Eng~neerzng, Princeton University, Princeton, New Jersey 085~0 Methods of achieving look-ahead in processing units are discussed. An optimality criterion is proposed, and several schemes are compared against the optimum under varying assumptions. These schemes include existing and proposed machine organizations, and theoretical treatments not mentioned before in this context. The problems of eliminating associative searches in the processor control and the handling of loop-forming decisions are also considered. The inherent limitations of such processors are discussed. Finally, a number of enhancements to look-ahead proces- sors is qualitatively surveyed. Keywords and Phrases: asynchronous computation, computer architecture, computer organization, look-ahead, parallelism, pipelining, schemata CR Categories: 5.24, 5.5, 6.32, 6.33 INTRODUCTION Arithmetic and logical processors in computers of the "second generation" and earlier tended to be unsophisticated insofar as their highly serial nature of instruction execution was concerned. Furthermore, the bottleneck created by a relatively slow core memory with a single-access port made the problem of enhancing the processor's speed uninteresting. With the advent of such techniques as multiple-port interleaved memories, semiconductor memories, and the use of more fast, local registers (either programmable or cache), we have the capability of transmitting operands and

Journal

ACM Computing Surveys (CSUR) – Association for Computing Machinery

Published: Dec 1, 1975

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