Introduction to the Special Issue on the 2008 Workshop on Design, Analysis, and Simulation of Chip Multiprocessors (dasCMP ™08) Norman P. Jouppi*, Rakesh Kumar+, and Dean Tullsen++ *Hewlett Packard Labs, norm.jouppi@hp.com +University of Illinois at Urbana-Champaign, rakeshk@illinois.edu ++University of California, San Diego, tullsen@cs.ucsd.edu Chip multiprocessor architectures are becoming increasingly attractive as an option to provide high instruction throughput while keeping power and complexity under control. Such architectures have also been shown to have scalability and productivity advantages. Multi-core processors are now mainstream. However, putting multiple cores on a die throws open several interesting research and design issues. From choosing the number of cores on the die to choosing the complexity of these cores, from constructing a chip multiprocessor out of off-the-shelf cores to creating a customized œmulti-core aware  multi-core design, there are several difficult questions that need to be addressed. Connecting the cores, determining the right memory subsystem, ensuring coherence and consistency of data, and trying to limit the area and power budgets, all require a deep understanding of issues and innovative application of ideas. Even simulating and evaluating a chip multiprocessor represents a significant challenge. There are equally interesting issues regarding programming and compilation for chip multiprocessors. All these questions and issues become more difficult and complicated for architectures with more than two cores. The goal of this workshop was to bring together researchers, computer architects, and engineers working on a broad spectrum of topics pertaining to the architecture, simulation, and design of chip multiprocessors. The workshop provided a forum for presenting and exchanging new ideas and experiences in this area and to discuss and explore hardware/software techniques and tools for efficient multi-core computation. We received many high quality submissions (13) for the workshop. Unfortunately even given a full-day workshop format, to allow time for discussion, a keynote, and breaks we were only able to accept 7 papers for presentation at the workshop. A successful workshop requires the help of many individuals. We would like to thank each of our program committee members for their quality reviews of workshop submissions: Krste Asanovic, Rajeev Balasubramonian, Manolis Katenvis, Stefanos Kaxiras, Christos Kozyrakis, Jim Laudon, Sally McKee, Martha Mercaldi, Chuck Moore, Ravi Nair, Ronny Ronen, Per Stenstrom, and David Wood. We would also like to thank Koen De Bosschere and Donald Yeung, the Micro-40 Workshops Co-chairs, for their help in organizing the workshop. And we would like to thank Antonio Gonzalez for giving the opening keynote of the workshop. Finally, we would like to thank the SIGARCH Computer Architecture News editor Doug DeGroot for all his help in putting together this special issue. We hope you find the papers of this fourth workshop to be intellectually stimulating, and that you will be inspired to contribute your ideas and efforts to future workshops! ACM SIGARCH Computer Architecture News Vol. 37, No. 2, May 2009

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