14 Introduction to Special Issue: Asynchrony in System Design Asynchronous or clockless design is currently poised to play a critical enabling role in microelectronic systems. Synchronous designers are increasingly contending with severe challenges: high-speed clock distribution, high power consumption, integrating multiple cores operating at different rates, and managing manufacturing and runtime variability. Asynchronous design abandons global clocking in favor of local handshake communication, thereby providing the potential for enhanced scalability and modularity, reduced switching activity, and graceful accommodation of delay variation. In the digital domain, a number of recent systems-on-chip (SoCs), composed of multiple cores, have already broken with the single-clock paradigm: Each chip typically contains several distinct clock domains, and the overall integration is asynchronous (i.e., elastic) in nature. In the realm of emerging technologies, even more extreme timing irregularities have been observed such that centralized clocking appears to be unrealistic. Hence, an asynchronous approach is likely to play a fundamental role in making these technologies feasible for assembling large-scale systems. This special issue of JETC presents several articles that highlight the state-of-theart of asynchrony in system design. Contributions were submitted by researchers from both industry and academia, and each article was selected through a rigorous review
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Introduction to Special Issue: Asynchrony in System Design
Singh, Montek; Nowick, Steven M.
Follow ACM Journal on Emerging Technologies in Computing Systems (JETC)
, Volume 7 (4)
Association for Computing Machinery – Dec 1, 2011
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