The memory bandwidth demands of modern microprocessors require the use of a multi-ported cache to achieve peak performance. However, multi-ported caches are costly to implement. In this paper we propose techniques for improving the bandwidth of a single cache port by using additional buffering in the processor, and by taking maximum advantage of a wider cache port. We evaluate these techniques using realistic applications that include the operating system. Our techniques using a single-ported cache achieve 91% of the performance of a dual-ported cache.
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Increasing cache port efficiency for dynamic superscalar microprocessors
Wilson, Kenneth M.; Olukotun, Kunle; Rosenblum, Mendel
Follow ACM SIGARCH Computer Architecture News
, Volume 24 (2)
Association for Computing Machinery – May 1, 1996
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