HALSIM--a very fast SPARC V9 Behavioral Model. David Barach, Jaspal Kohli, John Slice, Marc Spaulding, Rajeev Bharadhwaj, Don Hudson, Cliff Neighbors, Nirmal Saxena, and Rolland Crunk. HAL Computer Systems, Inc. 1315 Dell Ave. Campbell, CA 95008. (408) 379-7000 Abstract This paper describes several implementation techniques used in HAL's 250 KIPS SPARC V9 behavioral model. Beyond presenting the details of our processor model, we describe several areas of innovation: architectural state-vector capture for injection into a gate-level hardware model, using an EDC polynomial-based signature scheme to verify a hardware design; obtaining accurate kernel and user-mode instruction trace data. 1. Introduction In an era where time-to-market domintates other considerations in systems development, the HAL software group faced an interesting problem: to port SVR4/ES to SPARC V9, a 64-bit, unimplemented architecturemin parallel with ongoing hardware architecture and implementation activities. Evidently, we needed to construct a software model; however, as they say, the devil was decidedly in the details. Structurally, HALSIM's first processor model was an easy-to-modify predominantly C-language implementation. Since the SPARC V9 architecture committee changed the opcode maps with depressing regularity for quite some time, it proved very convenient to have an easily-modified processor model. [SPARC93] Unfortunately, the C-model proved
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HALSIM—a very fast SPARC V9 behavioral model
Barach, David; Kohli, Jaspal; Slice, John; Spaulding, Marc; Bharadhwaj, Rajeev; Hudson, Don; Neighbors, Cliff; Saxena, Nirmal; Crunk, Rolland
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, Volume 22 (1)
Association for Computing Machinery – Mar 1, 1994
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