Graffiti on "The M e m o r y Wall" Eric E. Johnson ParallelArchitecture Research Lab Klipsch School of Electricaland Computer Engineering N e w Mexico State University ejohnson@ nmsu.edu The paper "Hitting the M e m o r y Wail: Implications of the Obvious" by Wulf and M c K e e in the March 1995 issue of Computer Architecture News presented an interesting discussion of the bounds on processor performance imposed by m e m o r y performance. This note further examines that issue. As in the earlier paper, simple models are used, although with slightly different notation: tavg to RPI CPI the average m e m o r y access time in units of the processor clock cycle the access time of the top level of the m e m o r y hierarchy (level-1 cache) the average number of m e m o r y references for instructions, opcrands, and results made. by a processor for each instruction executed clock cycles per instruction completed CPI when tavg = to cPh Assuming a single processor port to memory, we have CPI = CPIo + RPI (tavg - to). (The situation is only slightly more
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Graffiti on “the memory wall”
Johnson, Eric E.
Follow ACM SIGARCH Computer Architecture News
, Volume 23 (4)
Association for Computing Machinery – Sep 1, 1995
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