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Fine-grain design space exploration for a cartographic SoC multiprocessor

Fine-grain design space exploration for a cartographic SoC multiprocessor Fine-Grain Design Space Exploration for a Cartographic SoC Multiprocessor Alessio Bechini, Pierfrancesco Foglia and Cosimo Antonio Prete Universit~l di Pisa Dipartimento di Ingegneria dell'lnformazione via Diotisalvi, 2 56126 PISA (Italy) {a.bechini, foglia, prete}@iet.unipi.it ABSTRACT Traditionally, in the field of embedded systems low power consumption and low cost have been always regarded as stringent specification constraints. In recent years, high computational power has become a fundamental requirement as well. This has been mainly determined by the introduction of new features, typical of general-purpose systems, e.g. GUI-based interfaces. In this setting, low cost, low power consumption, significant computational power and short time-to-market are conflicting needs that have to be accommodated. The adoption of a simple multiprocessor on a single chip can be deemed a convenient answer, because it is able to deliver a considerable computing power using low-cost and low-power CPU cores. In this paper, we take into account SPP, a cartographic system to be deployed on hand-held devices. We present the overall methodology used for designing the multiprocessor architecture of its hardware platform, and we focus on the activities that have been carried out to get to the more convenient setting for the system, respect to the specification requirements. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM SIGARCH Computer Architecture News Association for Computing Machinery

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