Exploiting Instruct ion-Level Parallelism: The Multithreaded Approach* Dept. Philip Lenir, R. Govindarajan and S.S. Nemawarkar of Electrical Engineering, McGill University, Montreal, H3A 2A7, CANADA {lenir@ee470,govindr@pike,shashank@pike}.ee.mcgill.ca Abstract The main challenge in the field of Very Large Instruction Word (VLIW) and superscalar architectures is exploiting as much instruction-level parallelism as possible. In this paper instruction an execution from model a set of which uses multiple instruction-level sequences and extracts parallelism at runtime enabled threads has been presented. A new multi-ring architecture has been proposed to support the execution model. data locality, tion which The (ii) multithreaded activations architecture buffer features and (i) large resident to improve program a novel high-speed zero load/store organizathe lo- ensures stalls for cal variables of an activation, and (iii) a dynamic instruction scheduler that groups operations from multiple threads for execution. ation studies predict Initial performance evaluis per cycle that the proposed architecture In this paper we propose a new approach based on the multithreaded execution model to exploit higher instruction-level parallelism. The multithreaded execution model [lo] has the potential to tolerate long and unpredictable memory latencies and to address the issues on synchronization costs in a satisfactory manner. In the proposed model, instructions from
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Exploiting instruction-level parallelism: the multithreaded approach
Lenir, Philip; Govindarajan, R.; Nemawarkar, S. S.
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, Volume 23 (1-2)
Association for Computing Machinery – Dec 10, 1992
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