HPSm is a single-chip microarchitecture designed and implemented at the University of California to achieve high performance. The approach is to exploit both vertical and horizontal concurracy in the microarchitecture. Experiments have been conducted to demonstrate the effectivenese of HPSm as compared is a popular single-chip microarchitecture, the Berkeley RISC/SPUR. Evaluations have been done with both central intensive and hosting point intensive benchmarks. For both types of benchmarks, we show that the HPSm microarchitecture achieves significant speedup ever the RISC/SPUR microarchitecture implemented with the same fabrication technology.
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Exploiting horizontal and vertical concurrency via the HPSm microprocessor
Hwu, Wen-mei W.; Patt, Yale N.
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, Volume 19 (3)
Association for Computing Machinery – Sep 1, 1988
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