Efficient Equivalence Checkng of Multi-Ph=e Designs Using Retiming ~ Gagan Hasteer Arnbit Design Systems gagan@ambit.com Anmol Nlathur Ambit Design Systems amathur@ambit .com Prithviraj Banerjee Northwestern University banerjee@ece.n~vu. edu Abstract The use of multi-phase clotilng scheme, aggressive pipelining and sparse encodings in high performance designs results in a tremendous increase in the state space. In this paper, we show that automatically transforming such dwigns to ones that have more dense encodings can result in significant benefits in using implicit BDD-based techniques for their verification. We formulate a relaxed retiming framework which is more powerful than traditional retiming in reducing the number of latches and show that it can be applied to the product machine model for cheWlng sequential hardwae equitience (SHE) without altering the correctness of the SHE check. We combine retiming v.tithphase abstraction [4] (a technique to transform multi-phase FShls to singlephase FSMS for equidence checking). The tivo transformations enable the SHE check to be performed on high performance controllers with large state space (more than 100 latches) from an industrid setting. Introduction Due to aggrmsive timing, many recent microprocessors use a multi-phase (most commonly ~~phase tith WO nonoverlapping complementary clocks) dwign methodology tith level
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Efficient equivalence checking of multi-phase designs using retiming
Hasteer, Gagan; Mathur, Anmol; Banerjee, Prithviraj
Association for Computing Machinery — Nov 1, 1998
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