In recent years, many advances have been made in the development of molecular scale devices. Experimental data shows that these devices have potential for use in both memory and logic. This article describes the challenges faced in building crossbar array-based molecular memory and develops a methodology to optimize molecular scale architectures based on experimental device data taken at room temperature. In particular, issues in reading and writing such as memory using CMOS are discussed, and a solution is introduced for easily reading device conductivity states (typically characterized by very small currents). Additionally, a metric is derived to determine the voltages for writing to the crossbar array. The proposed memory design is also simulated with consideration to device parameter variations. Thus, the results presented here shed light on important design choices to be made at multiple abstraction levels, from devices to architectures. Simulation results, incorporating experimental device data, are presented using Cadence Spectre.
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Designing CMOS/molecular memories while considering device parameter variations
Rose, Garrett S.; Yao, Yuxing; Tour, James M.; Cabe, Adam C.; Gergel-Hackett, Nadine; Majumdar, Nabanita; Bean, John C.; Harriott, Lloyd R.; Stan, Mircea R.
Follow ACM Journal on Emerging Technologies in Computing Systems (JETC)
, Volume 3 (1)
Association for Computing Machinery – Apr 1, 2007
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