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Journals ACM SIGARCH Computer Architecture News Volume 27 Issue 4

This paper contains corrections to published results on the RAMpage memory hierarchy. The originally published results contained erroneous values for cache miss penalties for a conventional cache architecture against which the RAMpage hierarchy was being compared. The incorrect results showed that RAMpage with context switches on misses to DRAM had similar performance to a conventional 2-way associative L2 cache-based hierarchy. The corrected results show that the RAMpage hierarchy in fact outperforms a conventional 2-way associative cache hierarchy by up to 29%, for the measured variations.

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Correction to RAMpage ASPOLOS paper

Machanick, Phillip
ACM SIGARCH Computer Architecture News , Volume 27 (4)
Association for Computing Machinery – Sep 1, 1999

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