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Journals ACM SIGARCH Computer Architecture News Volume 25 Issue 3

A cache design aimed to reduce cycle time, area, and miss rate simultaneously is proposed in this paper. A cache with path balancing table, skewing, and indirect tags can reduce cycle time, use less area, and reduce miss rate at the same time as compared with a baseline cache. From our simulation results, we propose cache design alternatives in achieving lower cycle time, lower miss rate, and using less area.

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Cache design with path balancing table, skewing and indirect tags

Jokinen, Tommi; Wang, Chia-Jiu
ACM SIGARCH Computer Architecture News , Volume 25 (3)
Association for Computing Machinery – Jun 1, 1997

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