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Journals ACM Computing Surveys (CSUR) Volume 25 Issue 3

Cache Coherence in Large-Scale Issues and Comparisons DAVID Department Shared-Memory Multiprocessors: J. LILJA of Electrical Englneemng, Untverslty of M[nnesota, Mlnneapolls, Mznnesota 55455 Due to data data spreading caches have among processors A wide ante and due to the in reducing cache coherence have problem, delay in been proposed makmg To help surveys to thenwhich or or the private not been as effective the average memory multiprocessors for mamtammg it difficult computer current deslgn possibly as in uniprocessors. cache coherence them perform variety of mechanisms m large-scale some of the and (1) the shared-memory trade-offs involved, several detection strategy, either multiprocessors, implications this strategy, such paper critical issues to compare architect cache These design and implementation identifies cokerence enforcement understand issues memory coherence mechanisms include: accesses that stale through as updating incoherent are detected cache entries statically at compile-time, dynamically mvalidatmg, at run-time; (2) the coherence used to ensure are never referenced by a processor; (3) how the preczslon of block-sharzng Implementation cost and performance cache block are used issues, szze affects the performance the performance strategies system system. hybrzd memory a single to compare znformatzon can be changed of the coherence mechamsm; of the memory and are presented

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Cache coherence in large-scale shared-memory multiprocessors: issues and comparisons

Lilja, David J.
ACM Computing Surveys (CSUR) , Volume 25 (3)
Association for Computing Machinery – Sep 1, 1993

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