C a c h e and M e m o r y H i e r a r c h y Design: A P e r f o r m a n c e - D i r e c t e d A p p r o a c h by Steven A.PrzybylsM Morgan Kaufmann Publishers, 1990,223 pages,ISBN 1-55860-136-8 As pointed out in a recent ISCA 94 panel, relatively very few computer engineers are likely to be involved in processor design. Many more are likely to be involved in the design o f a m e m o r y hierarchy configuration interfacing to an existing off-the-shelf processor. For such engineers, this book is mandatory. It is an excellent research monograph, stemming primarily fi'om the author's Ph.D. thesis at Stanford, dedicated to advanced design issues o f cache and m e m o r y hierarchies. In addition to the author's original work, the b o o k contains a summary o f the results o f other researchers in the same area. Most o f the material in the text appears for the first time within a book. The book consists o f six chapters and two appendices. Before starting the actual text, there is a very helpful four page list o f symbols. The first introductory chapter clarifies the concepts o f instruction count, cycles per instruction, and cycle time, and overviews the rest o f the book. Chapter 2 o n background material is essentially a brief terminology glossary and a literature overview. The glossary is missing an important term o f write-allocate, however, it is not an issue in the subsequent research results reported b y the author. The statement in the definition o f Main M e m o r y is misleading: "main memory, being the last level in any memory hierarchy". Any? W h y any simple PC has a hard disk, which is a secondary memory (SM). Perhaps the author should have said "last level in m e m o r y hierarchy models treated in this text". The third chapter defines the problem and the m e m o r y hierarchy models treated in this book. It also establishes the analytical model which serves as a basis for the studies reported in the subsequent chapters. This analytical model appears for the first time in a book. Chapters 4 and 5 are really the "meat" o f the text: they contain a very detailed cache hierarchy analysis, tabulation o f experimental results, and subsequent discussion. Chapter 4 is dedicated to design issues o f a single-Ievel cache. The author considers tradeoffs o f cache size vs. cycle time ( C P U and cache), set size (associativity), block (line) size, block size vs. fetch size, summarizing with the discussion o f a globally optimum cache design. The author uses results obtained from tracing experimentation as well as from the analytical model. Chapter 5 is dedicated to the same type in-depth analysis o f multi-level cache hierarchies. The author's implementation o f the dynamic programming approach (traditionally used in optimal control) in cache hierarchy design, is a particularly notable innovation presented in this book. Chapter 6 summarizes the results presented in the previous chapters, offering conclusions and suggestions for further research. O f particular use is the list o f 9 final design guidelines for cache and m e m o r y hierarchy configurations. These guidelines constitute a very helpful summary o f the most important points made in the text. One m a y use them as a quick reference after having read the book a long time ago, or instead o f reading the w h o l e book in detail (for busy readers who can not spare the time to read the whole book). The two appendices at the end o f the b o o k deal with validation o f the empirical results and modelling write strategy effects. The author presents a good reference list at the end. Practically all key papers in the cache area, published prior to this book, are referenced. The author m a y be less cognizant o f computer organization textbooks: he quotes the first edition (1978) o f the very popular Hamacher et al. text, which had a second edition in 1984 and a third in 1990. Despite the b o o k ' s overall excellence, it is felt that the author missed an excellent chance o f producing a comprehensive text on cache, which could supersede the use o f other sources. This does not happen. The author is very brief on basic, undergraduate material. In fact, he sends the unprepared reader to some basic texts in computer organiT~tion. Readers not well versed in cache principles, are still directed to the basic A.J.Smith paper [1], to be followed by this text. The text is o f course an excellent source for graduate students intent on research in related areas and for practicing engineers. References. [1] AJ.Smith, Cache Memories, A C M Computing Surveys, eel.14, no.3, pp.473-530, Sept.1982. Reviewed by Daniel Tabak, ECE Dept., George Mason University, Fairfax, VA 22030-4444 dtabak~offl.gmu.edu ~ 28 m

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