This paper investigates a class of main memory accesses ( invalid memory traffic ) that can be eliminated altogether. Invalid memory traffic is real data traffic that transfers invalid data. By tracking the initialization of dynamic memory allocations, it is possible to identify store instructions that miss the cache and would fetch uninitialized heap data. The data transfers associated with these initialization misses can be avoided without losing correctness. The memory system property crucial for achieving good performance under heap allocation is cache installation - the ability to allocate and initialize a new object into the cache without a penalty. Tracking heap initialization at a cache block granularity enables cache installation mechanisms to provide zero-latency prefetching into the cache. We propose a hardware mechanism, the Allocation Range Cache, that can efficiently identify initializing store misses to the heap and trigger cache installations to avoid invalid memory traffic. Results: For a 2MB cache 23% of cache misses (35% of compulsory misses) to memory are initializing the heap in the SPEC CINT2000 benchmarks. By using a simple base-bounds range sweeping scheme to track the initialization of the 64 most recent dynamic memory allocations, nearly 100% of all initializing store misses can be identified and installed in cache without accessing memory. Smashing invalid memory traffic via cache installation at a cache block granularity removes 23% of all miss traffic and can provide up to 41% performance improvement.
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Avoiding initialization misses to the heap
Lewis, Jarrod A.; Black, Bryan; Lipasti, Mikko H.
Follow ACM SIGARCH Computer Architecture News
, Volume 30 (2)
Association for Computing Machinery – May 1, 2002
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