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Avoiding conditional branches by code replication

Avoiding conditional branches by code replication Avoiding Conditional FRANK MUELLER Fachbereich Informatik Branches by Code Replication DAVID B. WHALLEY Department Florida of Computer Science State University U.S.A. Humboldt- Universitat zu Berlin Unter den Linden 6 10099 Berlin, Germany Tallahassee, FL 32306-4019, e-mail: whalley@cs.fsu. edu phone: (904) 644-3506 SUMMARY On-chip piler instruction caches are increasing that improve in size. Coma variperforits results when a routine site. Execution able for other the is inlined from more than one call is availunrolling branch performance optimizations body within benefits often occur since the [DaH88]. a loop. Loop This writers are exploiting this fact by applying the execution call and return are avoided and more information replicates instructions effective [HeP90]. performed [GoR90], ety of optimization mance of a program at the expense of increasing optimization code size. This paper describes can be used to avoid conditional code. where and for the The central the result to replicate for restructuring and for restructured of a conditional code the code. a new optimization that branches by replicating if there are paths will be known are these in the Algorithms to avoid that branch it. flow results applied branches reduces the number scheduling Replicating Software of compare of instructions portions pipelining and http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM SIGPLAN Notices Association for Computing Machinery

Avoiding conditional branches by code replication

Mueller, Frank; Whalley, David B.
ACM SIGPLAN Notices , Volume 30 (6) – Jun 1, 1995
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Publisher
Association for Computing Machinery
Copyright
Copyright © 1995 by ACM Inc.
ISSN
0362-1340
DOI
10.1145/223428.207116
Publisher site
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Abstract

Avoiding Conditional FRANK MUELLER Fachbereich Informatik Branches by Code Replication DAVID B. WHALLEY Department Florida of Computer Science State University U.S.A. Humboldt- Universitat zu Berlin Unter den Linden 6 10099 Berlin, Germany Tallahassee, FL 32306-4019, e-mail: whalley@cs.fsu. edu phone: (904) 644-3506 SUMMARY On-chip piler instruction caches are increasing that improve in size. Coma variperforits results when a routine site. Execution able for other the is inlined from more than one call is availunrolling branch performance optimizations body within benefits often occur since the [DaH88]. a loop. Loop This writers are exploiting this fact by applying the execution call and return are avoided and more information replicates instructions effective [HeP90]. performed [GoR90], ety of optimization mance of a program at the expense of increasing optimization code size. This paper describes can be used to avoid conditional code. where and for the The central the result to replicate for restructuring and for restructured of a conditional code the code. a new optimization that branches by replicating if there are paths will be known are these in the Algorithms to avoid that branch it. flow results applied branches reduces the number scheduling Replicating Software of compare of instructions portions pipelining and

Journal

ACM SIGPLAN Notices – Association for Computing Machinery

Published: Jun 1, 1995

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