Architectural Support for Cache Based Vector Computation C K Yuen (yuenck@comp.nus.edu.sg) School o f Computing National University of Singapore Kent Ridge, Singapore 119260 Abstract The possibility o f providing vector computation support to microprocessors is studied. It is suggested that frame registers pointing to vector elements stored in the cache can be used to stream data to and from vector arithmetic pipelines. 1. Introduction Over the past two decades, phenomenal progress took place in microprocessor architecture, making the single-chip CPUs almost as powerful as supercomputers. With further increases in chip complexity expectexi, it is practical to consider the inclusion of vector support in such systems soon, though one would expect that the methods used in the vector supercomputers [1][2][3] need to be modified in order to be applied to microprocessors. In particular, it may be difficult to adopt the vector registers that such supercomputers use, in view o f the demands they make on the chip surface area. This paper will discuss schemes whereby source and destination vectors can be accommodated in the cache rather than vector registers. That is, input data to the arithmetic pipelines are pumped out of the cache, and results axe returned to the
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Architectural support for the cache based vector computation
Yuen, C. K.
Follow ACM SIGARCH Computer Architecture News
, Volume 27 (3)
Association for Computing Machinery – Jun 1, 1999
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