The increased use of Hardware Description Languages (HDLs) in the process of designing digital systems has spawned an increased interest in the development of simulation systems for these HDLs. Unfortunately, the size and complexity of most contemporary digital systems is such that obtaining meaningful HDL simulation results may require days or even weeks of processing time. Thus, there is a growing need to speed-up the HDL simulation of digital systems at all levels of design abstractions. One promising approach is to depart from the von Neuman style of computation and use a general-purpose mutiprocessor system to simulate digital systems. As part of the research supported by SIGDA/DATC Design Automation Graduate Scholarship, we implemented a prototype distributed multi-level functional HDL simulator. The technique that we use to speed-up simulation is based on the Virtual Time algorithm.
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An investigation of the performance of a distributed functional digital simulator
Chawla, P.; Carter, H. W.
Follow ACM SIGDA Newsletter
, Volume 19 (2)
Association for Computing Machinery – Sep 1, 1989
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