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Journals ACM SIGDA Newsletter Volume 9 Issue 1

AN EVALUATION OF RANDOM INPUT TEST FOR THE VERIFICATION OF CIRCUIT REALIZATIONS Yoshiaki Wakimura & Yoshihiro Tohma Department of Computer Science Tokyo Institute of Technology, Tokyo, Japan ABSTRACT This paper evaluates the capability of a random input test for the verification that a given circuit correctly realizes its specification. i. INTRODUCTION It has been well recognized that the verification of circuit realizations is a very significant problem in manufacturing LSI circuits and the process of this verification should be included in the design automation of LSI. The more complicated the circuit configuration is, the more timeconsuming elaboration a deterministic test for verifying the circuit realization needs. Accordingly, a deterministic approach does not seem very practical, while a random input test may be feasible. So far, many papers on the detectability and the effectiveness of the random input test for faulty circuits have been published (1)-(5),(10), (ii) and several methods to enhance its effectiveness have also been proposed (6)-(9),(12). By virtue of the randomness of test inputs, however, a question remains how much confidence we can obtain on the correctness of circuit realization, even if a test does not detect the anomalism. In this paper, we evaluate the capability

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An evaluation of random input test for the verification of circuit realizations

Wakimura, Yoshiaki; Tohma, Yoshihiro
ACM SIGDA Newsletter , Volume 9 (1)
Association for Computing Machinery – Mar 1, 1979

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