A n E m p i r i c a l S t u d y on how P r o g r a m L a y o u t Affects C a c h e Miss R a t e s Jeffrey P. Bradford Electrical and Computer Engineering Purdue University West Lafayette, IN 47907 j e f f r e y , bradford~computer, org Russell Quong Sun Microsystems--SUN 03-201 430NMary Sunnyvale, CA 94086 quong@best.com Abstract Cache miss rates are quoted for a specific program, cache configuration, and input set; the effect of program layout on the miss rate has largely been ignored. This paper examines the miss variation, that is, the variation in the miss rate for instruction and data caches resulting from randomly generated layouts; the layouts were generated by changing the order of the modules on the command line when linking. This analysis is performed for several cache sizes, lines sizes, set-associativlties, input sets, compiler versions, and optimization levels for five programs in the SPECg2 benchmark suite. Miss rates were observed that varied from 60~ to 180~ of the mean miss rate. We did not observe any consistently good layouts across different parameters; in
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