Ultra High Speed Computing will be addressed in the form of a new computing architecture using networks of processors, program partition/allocation techniques, and with specific design elements of the type that would be used for database acceleration. This optimum networking architecture will merge commercially available components and support coordinated algorithms and software methodology to fully exploit potential gains in computational speed through parallel computing. The network of processors to be investigated will be of value at the fine grain level for computational processes and at the large grain level for database and communication processes. The complimentary relationship of dataflow and database technology will be sued to focus the investigations with an emphasis placed on hardware implementation. A Phase I program, described in this paper, would analyze the proposed architecture, including hardware and software tradeoffs, and would define an appropriate simulation based methodology for a future Phase II program in which the candidate designs would be tested.
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An eclectic 5th generation architecture for ultra high speed computing
Rouse, Larry O.; Forbes, John F.; Gaudiot, Jean-Luc
Follow ACM SIGART Bulletin
, Volume (95)
Association for Computing Machinery – Jan 1, 1986
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