An Aspect of ICCAD-89: An Attendee's R e p o r t Ankan K. Pramanick Department of Electrical and Computer Eng. The University of Iowa Iowa City, IOWA - 52242 I had an opportunity to attend this year's International Conference on Computer Aided Design, held at Santa Clam, Cafifornia, from the 6th. to the 9th. of November, where I was scheduled to present a paper. Being primarily interested in testing and Design For Testability (DFT), I was interested to find a relatively high number of technical sessions dealing with such issues. There were five sessions entirely devoted to testing, and several others that addressed in part many different issues in testing. From these sessions, and also from the tutorial on "New Trends in Testing and Verification" that I attended, an important aspect that seems to be evolving rapidly is Synthesis For Testability (SFT). With the advances in automated circuit design and IC technology, the problems of testing have become much more difficult because of the increase in functionality per chip, larger numbers of hierarchical design levels, and lowered observability at the accessible chip pins. Traditionally, synthesis has been aimed at optimizing chip area/delays. This year we saw several presentations that aimed at using aspects of synthesis specifically meant to increase the ease of testing of the designed chip, namely, the further evolution of SFT. These presentations demonslrated'how fresh synthesis approaches can produce both combinational and sequential circuits with very high levels of testability. These include design methodologies for the multifault testability of multilevel logic, design for testability of sequential machines at the logic synthesis level, and synthesis of delay fault testable combinational circuits. This trend of DFT starting at a relatively early level in the synthesis process, as opposed to commonly used DFT methodologies that rely on post-synthesis logic modifications, appears to be an important and rapidly evolving new aspect in logic design and testing. I think we can look forward to many interesting developments in SFT in the future. SIGDA Newsletter, vol 20, number I
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