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An algorithm for microcode compaction of VHDL behavioral descriptions

An algorithm for microcode compaction of VHDL behavioral descriptions We present as algorithm to transform a sequential (vertical microcode) VHDL (VHSIC Hardware Description Language) behavioral description of a digital system design into a parallel (horizontal microcode) VHDL description. Data dependency analysis is performed on the sequential code to identify the parallelism within the code. This parallel VHDL code is targeted for synthesis by the MIMOLA synthesis system. http://www.deepdyve.com/assets/images/DeepDyve-Logo-lg.png ACM SIGMICRO Newsletter Association for Computing Machinery

An algorithm for microcode compaction of VHDL behavioral descriptions

Bhasker, Jayaram
ACM SIGMICRO Newsletter , Volume 19 (1-2) – Jun 1, 1988
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References (3)

  • Aho A. (1979)

    7

    Principles of Compiler Design, Addison Wesley

  • Fisher J. A. (1981)

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    IEEE Transactions on Computers

  • Dasgupta S. (1976)

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    on Computers

Publisher
Association for Computing Machinery
Copyright
Copyright © 1988 by ACM Inc.
ISSN
1050-916X
DOI
10.1145/62197.62204
Publisher site
See Article on Publisher Site

Abstract

We present as algorithm to transform a sequential (vertical microcode) VHDL (VHSIC Hardware Description Language) behavioral description of a digital system design into a parallel (horizontal microcode) VHDL description. Data dependency analysis is performed on the sequential code to identify the parallelism within the code. This parallel VHDL code is targeted for synthesis by the MIMOLA synthesis system.

Journal

ACM SIGMICRO Newsletter – Association for Computing Machinery

Published: Jun 1, 1988

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