A PARTITIONING TECHNIQUE FOR LSI CHIPS Pao-Tsin Wang International Business Machines Corporation System Development Division 9500 Godwin Dr. Manassas, Va. 22110 I. Introduction A technique for partitioning LSI chips is presented in this paper. This technique is a refinement of the author's previous work [1]. The word "partitioning" is taken to mean the dividing of a chip into n sections. Each section will contain a group of circuits. The size of a section is defined as the amount of physical area occupied by the group of circuits. Each section does not have to be equal in size, however, the difference in size between any two sections should be within some prespecified number. Since the physical dimension of each circuit is not uniform, the number of circuits in a section may vary a great deal from section to section. A good partition is one such that each section has a valid size and the number of interconnections between any two sections is the smallest. In essence, one should attempt to achieve two goals in th e p r ocess of partztlonlng: . . . . ~-malntaln a valid size for each section and reduce ~he~be~f"~tersection connectlons as m u
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A partitioning technique for LSI chips
Wang, Pao-Tsin
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, Volume 4 (3)
Association for Computing Machinery – Sep 1, 1974
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