A New Architecture for FPGA based Implementation of Conversion of Binary to Double Base Number System (DBNS) using Parallel Search Technique Satrughna Singha [1], Aniruddha Ghosh [2] and Amitabha Sinha [3] JIS College of Engineering, Kalyani, Nadia, West Bengal, India Calcutta Institute of Technology, Uluberia, West Bengal, India West Bengal University of Technology, Salt Lake, Kolkata, India e-mail: [1] satrughna.singha@gmail.com. [2] g_aniruddha2003@yahoo.com [3] amitabha_sinha@wbut.ac.in. Abstract: Compute intensive signal Processing Algorithms demand efficient execution of high performance arithmetic operations. Since, double base number system (DBNS) offers high performance arithmetic units, it is gaining attention to many researchers .However, the advantage of DBNS can not be exploited due to large conversion time from binary to DBNS. Keeping this issue in view, this paper presents a novel conversion scheme using parallel search technique. . Index Terms - Double Base Number Systems (DBNS), Look-up Table, Binary Search Tree, Conversion Processing Element, Multiple Index DBNS. I. INTRODUCTION Signal processing algorithms are computationally intensive and therefore, the major issues have been the enhancement of speed of the arithmetic units in general and multiplications and additions in particular [1]. To improve the performance of adders and subtractors, a number of well known schemes have been
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A new architecture for FPGA based implementation of conversion of binary to double base number system (DBNS) using parallel search technique
Singha, Satrughna; Ghosh, Aniruddha; Sinha, Amitabha
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, Volume 39 (5)
Association for Computing Machinery – Jan 9, 2012
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