In this paper, a compiler optimization to reduce the execution time of loop nest is proposed. Loop tiling is used to optimize loop nest. Loop tiling is the well-known optimization for improving locality. However, it has a count result that increases the number of instructions to loop control. These increased instructions disturb the effect of locality optimization. Therefore, the tiling of innermost loop is not perform in order to reduce the instructions for loop control in this paper. This optimization consists of two steps. In the first step, loop permutation is used to maximize the spatial reuse of innermost loop. Because innermost loop tiling is not performed, spatial reuse of innermost loop is exploited to reduce execution time of loop nest. In the second step, the tile size of outer loops is decided using the basic cache parameters. When this optimization is applied to the matrix multiplication, execution time is improved 3 to 4 fold. Also, this optimization technique is easily applied to make a parallelizing and/or optimizing compilers.
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A compiler optimization to reduce execution time of loop nest
Kwon, Oh-Young; Park, Gi-Ho; Han, Tack-Don
Follow ACM SIGARCH Computer Architecture News
, Volume 24 (1)
Association for Computing Machinery – Mar 1, 1996
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