The goal for the Logic Level Modeling for ASICs Workshop was to provide an interchange of ideas between people working on ASIC logic level models. Logic Level Models use discrete values at discrete time steps. A simulation or analysis model performs an evaluation based upon values present at ports and upon internal state. Therefore, the workshop discussions centered upon topics related to simulation and analysis based upon discrete logic values and discrete time steps. The workshop goal was achieved by including people from ASIC foundries, CAE companies, and System designers (i.e. ASIC users.)
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1990 Workshop on Logic Level Modeling for ASICs final report
Glasser, Mark; Mathews, Rob; Acken, John M.
Follow ACM SIGDA Newsletter
, Volume 21 (1)
Association for Computing Machinery – Jun 1, 1991
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