Effects of gate-first and gate-last process on interface quality
of In
0.53
Ga
0.47
As metal-oxide-semiconductor capacitors using
atomic-layer-deposited Al
2
O
3
and HfO
2
oxides
Han Zhao,
1,a͒
Jeff Huang,
2
Yen-Ting Chen,
1
Jung Hwan Yum,
1
Yanzhen Wang,
1
Fei Zhou,
1
Fei Xue,
1
and Jack C. Lee
1
1
Department of Electrical and Computer Engineering, The University of Texas at Austin, Texas 78758, USA
2
Sematech, Austin, Texas 78741, USA
͑Received 25 August 2009; accepted 19 November 2009; published online 22 December 2009͒
We have investigated the effects of gate-first and gate-last process on oxide/InGaAs interface
quality using In
0.53
Ga
0.47
As metal-oxide-semiconductor capacitors ͑MOSCAPs͒ with
atomic-layer-deposited ͑ALD͒ oxides. Sequence of source/drain activation anneal in the process
results in remarkable electrical and physical difference. Applying gate-last process provides
significant frequency dispersion reduction and interface trap density reduction for InGaAs
MOSCAPs compared to gate-first process. A large amount of In–O, Ga–O, and As–As bonds was
observed on InGaAs surface after gate-first process while no detectable interface reaction after
gate-last process. Electrical and physical results also show that ALD Al
2
O
3
exhibits better interface
quality on InGaAs than HfO
2
.©2009 American Institute of Physics. ͓doi:10.1063/1.3275001͔
III-V based metal-oxide-semiconductor ͑MOS͒ devices
have attracted a great deal of interest due to the higher elec-
tron mobility than silicon. However, the lack of high quality,
thermodynamically stable insulators that passivate the inter-
face imposes the major challenge in implementing III-V
metal-oxide-semiconductor transistors ͑MOSFETs͒ into
complementary MOS technology. Recently, surface-channel
inversion-mode InGaAs MOSFETs with atomic layer de-
posited ͑ALD͒ Al
2
O
3
, HfO
2
, and ZrO
2
dielectrics,
1–3
mo-
lecular beam epitaxy Ga
2
O
3
͑Gd
2
O
3
͒ dielectrics
4
and Si
passivation layer/high-
gate stacks
5
show promising results
on MOSFETs with high drive current capability. Buried
channel InGaAs MOSFETs or MOS high-electron-mobility
transistors
6–10
demonstrate even much higher drive current
density and channel mobility. Surface-channel inversion-type
MOSFETs are preferred over buried-channel depletion-type
MOSFETs because of their superior immunity to drain-
induced-barrier-lowing effects, and punch-through leakage
and breakdown problems. Source and drain ͑S/D͒ usually
need to be formed by ion implantation and thermal activation
for surface-channel inversion-mode MOSFETs. However,
dielectric/semiconductor interface quality may degrade dur-
ing this high temperature S/D activation annealing process
for III-V MOS structure.
In this letter, we applied S/D activation process on
metal-oxide-semiconductor capacitors ͑MOSCAPs͒ to inves-
tigate the effect of this process on oxide/III-V interface qual-
ity. We compared the interface quality of In
0.53
Ga
0.47
As
MOSCAPs with ALD Al
2
O
3
and HfO
2
oxides under three
process conditions as follows: ͑a͒ only postdeposition an-
nealing ͑PDA-only͒, no S/D activation, ͑b͒ gate-first ͑G-first͒
process ͑S/D activated after gate stack deposition͒,
11
and ͑c͒
gate-last ͑G-last͒ process ͑S/D activated before gate stack
deposition͒.
1
It has been found that MOSCAPs with G-last
process can maintain similar interface trap density ͑D
it
͒ as
PDA-only samples, while the ones with G-first process have
much larger D
it
. This suggests that G-last process is
more promising for surface-channel inversion-type III-V
MOSFETs. Moreover, D
it
is higher for MOSCAPs with HfO
2
oxide than with Al
2
O
3
. X-ray photoelectron spectroscopy
͑XPS͒ indicates that G-first process results in a larger amount
of In–O, Ga–O, and As–As bonds on InGaAs surface, while
G-last process maintains similar surface chemical bonding
condition as PDA-only process. MOSCAPs with HfO
2
ex-
hibit more Ga–O bonds than the ones with Al
2
O
3
and similar
a͒
Electronic mail: zhaohan@mail.utexas.edu.
TABLE I. Process flow chart.
PDA-only G-first G-last
1. Wafer cleaning and S passivation 1. Wafer cleaning and S passivation 1. Wafer cleaning and S passivation
2. ALD gate dielectrics 2. ALD gate dielectrics 2. 10 nm ALD Al
2
O
3
capping layer
3. PDA at 500 °C, 90s in N
2
3. PDA at 500 °C, 90s in N
2
3. S/D activation at 700 °C, 10s in N
2
4. TaN gate metal and backside metal deposition 4. TaN gate metal deposition 4. Remove capping layer
5. S/D activation at 700 °C, 10s in N
2
5. Wafer cleaning and S passivation
6. Backside metal deposition 6. ALD gate dielectrics
7. PDA at 500 °C, 90s
8. TaN gate metal and backside metal
APPLIED PHYSICS LETTERS 95, 253501 ͑2009͒
0003-6951/2009/95͑25͒/253501/3/$25.00 © 2009 American Institute of Physics95, 253501-1